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October 2000
(R)
AS6WA5128
3.0V to 3.6V 512K x 8 IntelliwattTM low-power CMOS SRAM Features
* AS6WA5128 * IntelliwattTM active power circuitry * Industrial and commercial temperature ranges available * Organization: 524,288 words x 8 bits * 3.0V to 3.6V at 55 ns * Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
* 1.2V data retention * Equal access and cycle times * Easy memory expansion with CS, OE inputs * Smallest footprint packages
- 36(48)-ball FBGA - 32-pin TSOP I and TSOP II packages are available on Alliance AS6UB5128 product family (available January 2001)
* Low power consumption: STANDBY
- 72 W max at 3.6V
* ESD protection 2000 volts * Latch-up current 200 mA
Logic block diagram
VCC GND Input buffer
36(48)-CSP BGA Package (shading indicates no ball)
1 A A0 I/O5 I/O6 VSS VCC I/O7 I/O8 A9 B C D
I/O1
2 A1 A2
3 NC WE NC
4 A3 A4 A5
5 A6 A7
6 A8 I/O1 I/O2 VCC VSS
A0 A1 A2 A3 A4 A5 A6 A7 A8
Row decoder
Sense amp
512K x 8 Array (4,194,304)
I/O8
E F G H
Column decoder A9 A10 A11 A12 A13 A14 A15 A16
Control circuit
WE OE CS
A18 OE A10 CS A11
A17 A16 A12 A15 A13
I/O3 I/O4 A14
Selection guide
VCC Range Product AS6WA5128 Min (V) 3.0 Typ2 (V) 3.3 Max (V) 3.6 Speed (ns) 55 Power Dissipation Standby (ISB1) Operating (ICC) Max (mA) Max (A) 2 20
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ALLIANCE SEMICONDUCTOR
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Copyright (c)2000 Alliance Semiconductor. All rights reserved.
AS6WA5128
(R)
Functional description
The AS6WA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288 words x 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, the device enters standby mode: the AS6WA5128 is guaranteed not to exceed 72 W power consumption at 3.6V and 55ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable ( WE) and chip select (CS) low. Data on the input pins I/O1-I/O8 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. The device is available in the JEDEC standard 36(48)-ball FBGA package.
Absolute maximum ratings
Parameter Voltage on VCC relative to V SS Voltage on any I/O pin relative to GND Power dissipation Storage temperature (plastic) Temperature with VCC applied DC output current (low) Device Symbol VtIN VtI/O PD Tstg Tbias IOUT Min -0.5 -0.5 - -65 -55 - 1.0 +150 +125 20 Max VCC + 0.5 Unit V V W C C mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this spec ification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS H L L L L WE X X H H L OE X X H L X Supply Current ISB ISB ICC ICC ICC I/O1-I/O8 High Z High Z High Z DOUT DIN Mode Standby (ISB) Standby (ISB) Output disable (ICC) Read (ICC) Write (ICC)
Key: X = Don't care, L = Low, H = High.
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ALLIANCE SEMICONDUCTOR
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AS6WA5128
(R)
Recommended operating condition (over the operating range)
Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Output Load Current VCC Operating Supply Current IOH = -2.1mA IOL = 2.1mA Test Conditions VCC = 3.0V VCC = 3.0V VCC = 3.0V VCC = 3.0V GND < VIN < VCC GND < VO < VCC; Outputs High Z CS = VIL, IOUT = 0mA, f = 0, VIN = VIL or VIH VCC = 3.6V 2.2 -0.5 -1 -1 Min 2.4 0.4 VCC + 0.5 0.8 +1 +1 2 Max Unit V V V V A A mA
ICC1 @ 1 MHz
CS < 0.2V, VIN < Average VCC Operating 0.2V, Supply Current at 1 or VIN > VCC - 0.2V, MHz f = 1 mS Average VCC Operating CS VIL, V IN = VIL Supply Current or VIH, f = f Max
VCC = 3.6V
5
mA
ICC2
VCC = 3.6V (55 ns)
40
mA
ISB
CS Power Down Current; TTL Inputs
CS > V IH, other inputs = 0V - VCC CS > VCC - 0.2V, other inputs = 0V - VCC, f = fMax CS > VCC - 0.1V, f=0
VCC = 3.6V
100
A
ISB1
CS Power Down Current; CMOS Inputs
VCC = 3.6V
20
A
ISBDR
Data Retention
VCC = 1.2V
2
A
Capacitance (f = 1 MHz, Ta = Room temperature, VCC = NOMINAL)2
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CS, WE, OE I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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ALLIANCE SEMICONDUCTOR
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AS6WA5128
(R)
Read cycle (over the operating range)3,9
Parameter Read cycle time Address access time Chip select (CS) access time Output enable (OE) access time Output hold from address change CS low to output in low Z CS high to output in high Z OE low to output in low Z OE high to output in high Z Power up time Power down time Symbol tRC tAA tACS tOE tOH tCLZ tCHZ tOLZ tOHZ tPU tPD Min 55 - - - 10 10 0 5 0 0 - Max - 55 55 25 - - 20 - 20 - 55 Unit ns ns ns ns ns ns ns ns ns ns ns 5 4, 5 4, 5 4, 5 4, 5 4, 5 4, 5 3 3 Notes
Key to switching waveforms
Rising input Falling input Undefined/don't care
Read waveform 1 (address controlled)3,6,7,9
tRC Address tOH DOUT Previous data valid tAA Data valid tOH
Read waveform 2 (CS, OE controlled)3,6,8,9
tRC1 CS tOE OE tOLZ tACE DOUT tCLZ Supply current tPU 50% Data valid tPD 50% ICC ISB tOHZ tCHZ
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ALLIANCE SEMICONDUCTOR
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AS6WA5128
(R)
Write cycle (over the operating range)11
Parameter Write cycle time Chip select to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Min 55 40 40 0 35 0 25 0 0 5 Max - - - - - - - - 20 - Unit ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 Notes
Write waveform 1 (WE controlled)10,11
tWC tAW Address tWP WE tAS DIN tWZ DOUT tDW Data valid tOW tDH tAH
Write waveform 2 (CS controlled)10,11
tWC tAW Address tAS CS tWP WE tWZ DIN DOUT tDW Data valid tDH tCW tAH
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ALLIANCE SEMICONDUCTOR
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AS6WA5128
(R)
Data retention characteristics (over the operating range) 13,5
Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Symbol VDR ICCDR tCDR tR Test conditions VCC = 1.2V CS VCC - 0.1V or VIN VCC - 0.1V or VIN 0.1V Min 1.2V - 0 tRC Max 3.6 4 - - ns Unit V mA
Data retention waveform
Data retention mode VCC VCC tCDR CS VIH VDR VIH VDR 1.2V VCC tR
AC test loads and waveforms
VCC OUTPUT 30 pF R2 INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE R1 VCC OUTPUT 5 pF R2 VCC Typ GND (b) Thevenin equivalent: R1 OUTPUT ALL INPUT PULSES 90% 10% < 5 ns (c) 90% 10% RTH V
(a)
Parameters R1 R2 RTH VTH Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VCC = 3.0V 1105 1550 645 1.75V
VCC = 2.5V 16670 15380 8000 1.2V
VCC = 2.0V 15294 11300 6500 0.85V
Unit Ohms Ohms Ohms Volts
During VCC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS and OE are LOW for read cycle. Address valid prior to or coincident with CS transition LOW. All read cycle timings are referenced from the last valid address to the first transitioning address. CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. 1.2V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at high Z and low Z parameters, where C = 5pF.
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ALLIANCE SEMICONDUCTOR
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AS6WA5128
(R)
Typical DC and AC characteristics
Normalized supply current vs. supply voltage 1.4 1.2 Normalized TAA Normalized ISB2 Normalized ICC 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 3.7 VIN = VCC typ TA = 25 C 0.75 TA = 25 C 0.5 1.0 Normalized access time vs. supply voltage 3.0 2.5 2.0 1.5 1.0 0.5 0.0 VCC = VCC typ VIN = VCC typ Normalized standby current vs. ambient temperature
0.25 0.0 1.7
-0.5
2.2 2.7 3.2 3.7
-55
Supply voltage (V) Normalized standby current vs. supply voltage 1.4 1.2 Normalized ISB 1.0 0.8 0.6 0.4 0.2 0.0 1 2.8 1.9 Supply voltage (V) 3.7 VIN = VCC typ TA = 25 C ISB2
Supply Voltage (V)
25 105 Ambient temperature (C) Normalized ICC vs. Cycle Time
1.5 VIN = 3.6V TA = 25 C
Normalized ICC
1.0
0.50
0.10 1 5 10 Supply voltage (V) 15
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ALLIANCE SEMICONDUCTOR
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AS6WA5128
(R)
Package diagrams and dimensions
36(48)-ball FBGA Bottom View 6 5 4 3 2 1 Ball #A1 Top View Ball #A1 index
A B C D E F G H Elastomer A B1 B A1 C1 SRAM Die C
Side View E2 E E Die E1 D E2
Detail View A Y Die 0.3/Typ
Minimum A B B1 C C1 D E E1 E2 Y - 6.90 - 10.90 - 0.30 - - 0.22 -
Typical 0.75 7.00 3.75 11.00 5.25 0.35 - 0.68 0.25 -
Maximum - 7.10 - 11.10 - 0.40 1.20 - 0.27 0.08 Notes 1. Bump counts: 36(48) (8 row x 6 column). 2. Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are 0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max).
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ALLIANCE SEMICONDUCTOR
10/6/00
AS6WA5128
(R)
Ordering codes
Speed (ns) 55 55
Ordering Code
AS6WA5128-BC AS6WA5128-BI
Package Type
48-ball fine pitch BGA 48-ball fine pitch BGA
Operating Range Commercial
Industrial
Part numbering system
AS6WA SRAM IntelliwattTM prefix 5128 Device number T, ST, HF, HR, B Package: B: CSP BGA C, I Temperature range: C: Commercial: 0 C to 70 C I: Industrial: -40C to 85 C
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ALLIANCE SEMICONDUCTOR
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Copyright (c) 2000. Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and IntelliwattTM are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this web site and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and discl aims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indem nify Alliance against all claims arising from such use.

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